| Paper: | DISPS-P2.1 |
| Session: | DSP Algorithm Implementation in Hardware and Software |
| Location: | Poster Area G |
| Session Time: | Friday, May 31, 08:00 - 10:00 |
| Presentation Time: | Friday, May 31, 08:00 - 10:00 |
| Presentation: |
Poster
|
| Topic: |
Design and Implementation of Signal Processing Systems: DSP algorithm implementation in hardware and software |
| Paper Title: |
41.7BN-PIXELS/S RECONFIGURABLE INTRA PREDICTION ARCHITECTURE FOR HEVC 2560X1600 ENCODER |
| Authors: |
Zhenyu Liu, Dongsheng Wang, Tsinghua University, China; Hongxiang Zhu, Xiaodong Huang, Northwestern Polytechnical University, China |
