Technical Program

Paper Detail

Paper:DISPS-P1.8
Session:Design Methods for DSP Systems
Location:Poster Area F
Session Time:Friday, May 31, 08:00 - 10:00
Presentation Time:Friday, May 31, 08:00 - 10:00
Presentation: Poster
Topic: Design and Implementation of Signal Processing Systems: Algorithm and architecture co-optimization
Paper Title: CYCLE EFFICIENT BIT RATE MATCHING FOR LTE-A WITH INSRUCTIONS SUPPORT
Authors: Jui-Chieh Lin, Yu Hen Hu, University of Wisconsin-Madison, United States