DISPS-L1: VLSI Implementations |
| Session Type: Lecture |
| Time: Friday, May 31, 10:30 - 12:30 |
| Location: Room 121/122 |
| Session Chairs: Zhiyuan Yan, Lehigh University, Bethlehem, PA and Mohammad Mansour, American University of Beirut, Lebanon
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DISPS-L1.1: DATA STORAGE TIME SENSITIVE ECC SCHEMES FOR MLC NAND FLASH MEMORIES |
| Chengen Yang; Arizona State University |
| Deepak Muckatira; Arizona State University |
| Aditya Kulkarni; Arizona State University |
| Chaitali Chakrabarti; Arizona State University |
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DISPS-L1.2: SOFT-DECISION DECODING WITH CELL TO CELL INTERFERENCE REMOVED SIGNAL IN NAND FLASH MEMORY |
| Dong-Hwan Lee; Seoul National University |
| Wonyong Sung; Seoul National University |
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DISPS-L1.3: REDUCED-COMPLEXITY BINARY-WEIGHT-CODED ASSOCIATIVE MEMORIES |
| Hooman Jarollahi; McGill University |
| Naoya Onizawa; McGill University |
| Vincent Gripon; McGill University |
| Warren J. Gross; McGill University |
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DISPS-L1.4: EFFICIENT VLSI IMPLEMENTATION OF REDUCED-STATE SEQUENCE ESTIMATION FOR WIRELESS COMMUNICATIONS |
| Stefan Zwicky; Swiss Federal Institute of Technology, Zurich |
| Christian Benkeser; Swiss Federal Institute of Technology, Zurich |
| Andreas Burg; Swiss Federal Institute of Technology, Lausanne |
| Qiuting Huang; Swiss Federal Institute of Technology, Zurich |
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DISPS-L1.5: A SUB-100-MILLIWATT DUAL-CORE HOG ACCELERATOR VLSI FOR REAL-TIME MULTIPLE OBJECT DETECTION |
| Kenta Takagi; Kobe University |
| Kosuke Mizuno; Kobe University |
| Shintaro Izumi; Kobe University |
| Hiroshi Kawaguchi; Kobe University |
| Masahiko Yoshimoto; Kobe University |
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DISPS-L1.6: A COMPACT PROGRAMMABLE ANALOG CLASSIFIER USING A VMM + WTA NETWORK |
| Shubha Ramakrishnan; Georgia Institute of Technology |
| Jennifer Hasler; Georgia Institute of Technology |
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