| Paper: | DISPS-L1.4 |
| Session: | VLSI Implementations |
| Location: | Room 121/122 |
| Session Time: | Friday, May 31, 10:30 - 12:30 |
| Presentation Time: | Friday, May 31, 11:30 - 11:50 |
| Presentation: |
Lecture
|
| Topic: |
Design and Implementation of Signal Processing Systems: Algorithm and architecture co-optimization |
| Paper Title: |
EFFICIENT VLSI IMPLEMENTATION OF REDUCED-STATE SEQUENCE ESTIMATION FOR WIRELESS COMMUNICATIONS |
| Authors: |
Stefan Zwicky, Christian Benkeser, Swiss Federal Institute of Technology, Zurich, Switzerland; Andreas Burg, Swiss Federal Institute of Technology, Lausanne, Switzerland; Qiuting Huang, Swiss Federal Institute of Technology, Zurich, Switzerland |
