My ICASSP 2013 Schedule

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Paper Detail

Paper:.8
Session:Design Methods for DSP Systems
Session Time:Friday, May 31, 08:00 - 10:00
Presentation Time:Friday, May 31, 08:00 - 10:00
Presentation: Poster
Topic: Design and Implementation of Signal Processing Systems: Algorithm and architecture co-optimization
Paper Title: CYCLE EFFICIENT BIT RATE MATCHING FOR LTE-A WITH INSRUCTIONS SUPPORT
Authors: Jui-Chieh Lin; University of Wisconsin-Madison 
 Yu Hen Hu; University of Wisconsin-Madison