My ICASSP 2013 Schedule

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DISPS-P2: DSP Algorithm Implementation in Hardware and Software

Session Type: Poster
Time: Friday, May 31, 08:00 - 10:00
Location: Poster Area G
Session Chairs: Ching-Te Chiu, National Tsing Hua University, Hsinchu, Taiwan and Mickaƫl Raulet, IETR-INSA, Rennes, France
 
  DISPS-P2.1: 41.7BN-PIXELS/S RECONFIGURABLE INTRA PREDICTION ARCHITECTURE FOR HEVC 2560X1600 ENCODER
         Zhenyu Liu; Tsinghua University
         Dongsheng Wang; Tsinghua University
         Hongxiang Zhu; Northwestern Polytechnical University
         Xiaodong Huang; Northwestern Polytechnical University
 
  DISPS-P2.2: 4X4/8X8/12X12 RECONFIGURABLE MIMO DETECTOR ON MULTI-CORE DSP BASED ON EIGEN DECOMPOSITION OF DATAFLOW GRAPH
         Sheng-Hung Wu; National Tsing Hua University
         Chien-Yu Kao; Industrial Technology Research Institute
         Jen-Yuan Hsu; Industrial Technology Research Institute
         Pang-An Ting; Industrial Technology Research Institute
         Gwo-Giun Lee; National Cheng Kung University
         Yuan-Hao Huang; National Tsing Hua University
 
  DISPS-P2.3: A PARALLEL IMPLEMENTATION METHOD OF FFT-BASED FULL-SEARCH BLOCK MATCHING ALGORITHMS
         Toshiyuki Dobashi; Tokyo Metropolitan University
         Hitoshi Kiya; Tokyo Metropolitan University
 
  DISPS-P2.4: A NOVEL AND EFFICIENT MULTI-RESOLUTION CHANNELIZER FOR SOFTWARE DEFINED RADIO
         Fred Harris; San Diego State University
         Elettra Venosa; San Diego State University
         Xiaofei Chen; San Diego State University
         Chris Dick; Xilinx
         Brent Adams; Raytheon
 
  DISPS-P2.5: ARCHITECTURE OPTIMIZATIONS FOR BP POLAR DECODERS
         Bo Yuan; University of Minnesota, Twin cities
         Keshab K. Parhi; University of Minnesota, Twin cities
 
  DISPS-P2.6: FAST PCA-BASED FACE RECOGNITION ON GPUS
         Youngsang Woo; University of Seoul
         Cheongyong Yi; University of Seoul
         Youngmin Yi; University of Seoul
 
  DISPS-P2.7: PROGRAMMABLE LOW POWER IMPLEMENTATION OF THE HEVC ADAPTIVE LOOP FILTER
         Ilkka Hautala; University of Oulu
         Jani Boutellier; University of Oulu
         Jari Hannuksela; University of Oulu
 
  DISPS-P2.8: PROCESSOR BASED 20MHZ 4X4 CAT-5 LTE MIMO RECEIVER WITH ADVANCED DETECTORS
         Min Li; IMEC vzw
         Amir Amin; IMEC
         Rodolfo Torrea; IMEC
         Ubaid Ahmad; IMEC
         Raf Appeltans; IMEC
         Antoine Dejonghe; IMEC
         Liesbet Van Der Perre; IMEC
 
  DISPS-P2.9: A FAST AND EFFICIENT SIFT DETECTOR USING THE MOBILE GPU
         Blaine Rister; Rice University
         Guohui Wang; Rice University
         Michael Wu; Rice University
         Joseph R. Cavallaro; Rice University
 
  DISPS-P2.10: IMPLEMENTATION TRADE-OFFS FOR LINEAR DETECTION IN LARGE-SCALE MIMO SYSTEMS
         Bei Yin; Rice University
         Michael Wu; Rice University
         Christoph Studer; Rice University
         Joseph R. Cavallaro; Rice University
         Chris Dick; Xilinx
 
  DISPS-P2.11: GPU BASED IMPLEMENTATION OF RECURSIVE DIGITAL FILTERING ALGORITHMS
         Dong-Hwan Lee; Seoul National University
         Wonyong Sung; Seoul National University
 
  DISPS-P2.12: PORTABLE PARALLEL KERNELS FOR HIGH-SPEED BEAMFORMING IN SYNTHETIC APERTURE ULTRASOUND IMAGING
         Joao Amaro; University of Coimbra
         Gabriel Falcao; University of Coimbra
         Billy Y. S. Yiu; Medical Engineering Program, The University of Hong Kong
         Alfred C. H. Yu; Medical Engineering Program, The University of Hong Kong
 
  DISPS-P2.13: HARDWARE-EFFICIENT STEREO ESTIMATION USING A RESIDUAL-BASED APPROACH
         Abhishek A. Sharma; Carnegie Mellon University
         Kaustubh Neelathalli; Carnegie Mellon University
         Diana Marculescu; Carnegie Mellon University
         Eriko Nurvitadhi; Intel Science & Technology Center on Embedded Computing